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I use verilog-mode for both Verilog (extension .v) and System Verilog (extension .sv). I want to disable flycheck for .v files only. (Because they are typically multi-gigabyte netlists that take lots of CPU to process and I'm on a shared system.)

Is there a way of turning flycheck off in verilog mode when the extension is .v but not when it is .sv, while continuing to use verilog-mode for both? (And more generally for extensions that use the same mode.)

  • I think the more relevant question is: how do you turn flycheck mode on? It is not on by default for Verilog (.v) files, so you must be doing something to turn it on in your init file(s). Find that place and add your additional criteria before you turn it on. If you don't know how to do that, edit your queston and add the code in your init file that turns flycheck on: somebody here should be able to tell you how to proceed from that point. – NickD Oct 2 '19 at 22:11

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