I am using
outshine to organize my code (verilog/systemverilog language).
Here is an example use:
// * Class definition class my_class extends my_base_class; // code .. // ** Task 1 definition virtual task my_task1; // code .. endtask // ** Task 2 definition virtual task my_task2; // code .. endtask endclass
// ** Task 1 definition and
// ** Task 2 definition headers will not be detected as headers by the
outline-mode code as they are auto-indented by my language major-mode:
Is it possible to tame the indentation logic to NOT certain lines; in this case, they would be the lines beginning with
I have mentioned
verilog-mode in this question but this can be a generic problem too, on how to make the indentation ignore certain lines irrespective of the major mode.
Thanks to @glucas's answer, I now have the complete solution (my verilog setup on github) to this long-time problem!