Questions tagged [verilog]

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votes
3answers
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Verilog mode to navigate from begin to end

I am using verilog mode for Emacs. I am trying to find which begin is paired with which end. Is there any way to do this in Emacs?
2
votes
2answers
306 views

Disable “Autocompletion”/“Abbreviation” in Verilog-Mode

When I use the Verilog Mode in spacemacs with evil keybindings, every time I type e.g. wire and press ESC, an automatic dialouge pops up and asks me msb:, lsb: and name (RET to end). This is super ...
2
votes
1answer
460 views

Redefine verilog-mode header skeleton

The verilog-mode package contains this code: (define-skeleton verilog-sk-header-tmpl "Insert a comment block containing the module title, author, etc." "[Description]: " "// ...
4
votes
2answers
512 views

Configure indentation logic to ignore certain lines?

I am using outshine to organize my code (verilog/systemverilog language). Here is an example use: // * Class definition class my_class extends my_base_class; // code .. // ** Task 1 ...
8
votes
4answers
446 views

How do I disable ffap (find file at point) when the first two non-space characters in a line are '//'?

In Verilog/C/C++, comments can begin with //. Here's an example comment, //This is a comment I like to use the find-file-at-point feature. If my cursor is on the file name in `include "some_file.v"....